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| W528XXX DESIGN GUIDE ADPCM VOICE SYNTHESIZER (PowerSpeechTM ) TM INTRODUCTION The W528xxx family are programmable speech synthesis ICs that utilize the ADPCM coding method to generate all types of voice effects. The W528xxx's LOAD and JUMP commands and four programmable registers provide powerful userprogrammable functions that make this chip suitable for an extremely wide range of speech IC applications. Before developing their own PowerSpeechTM programs and codes, customers should review the application notes presented below. The W528xxx family includes the W528S03, W528S05, W528S08, W528S10, W528S12, W528S15, W528S20, W528S25, W528S30,W528S40,W528S50 and W528S60. The ROM size of each of these products is shown below: BODY W528S03 W528S05 W528S08 W528S10 W528S12 W528S15 Duration ROM Size(bit) BODY 3 Sec 96K W528S20 5 Sec 128K W528S25 8 Sec 288K W528S30 10 Sec 336K W52840 12 Sec 384K W528S50 15 Sec 480K W528S60 Duration ROM Size(bit) 20 Sec 576K 25 Sec 672K 30 Sec 768K 40 Sec 1216K 50 Sec 1376K 60 Sec 1536K FEATURES * * * * * * * * * * Programmable speech synthesizer Wide operating voltage range: 2.4 to 5.5 volts 4-bit ADPCM synthesis method Provides 4 direct trigger inputs that can easily be extended to 8 or 12 matrix trigger inputs Two trigger input debounce times ( Long/ Short ) can be set Provides up to 2 LEDs and 3 STOP outputs Every LED pin can drive 3 LEDs simultaneously LED flash frequency: 3 Hz AUD output current: 5 mA Flexible functions programmable through the following: - LD (load), JP (jump) commands - Four registers: R0, EN, STOP, and MODE - Conditional instructions - Speech equation - END instruction Public Release Date: March 1999 Revision A1 -1- W528XXX DESIGN GUIDE - Global repeat setting - Output frequency and LED flash type setting * * Programmable power-on initialization (POI) (can be interrupted by trigger inputs) POI delay time of 160 mS ensures stable voltage when chip is powered on * Can be programmed for the following functions: - Interrupt or non-interrupt for rising or falling edge of each trigger pin (this feature determines retriggerable, non-retriggerable, overwrite, and non-overwrite features of each trigger pin) - Four playing modes: One Shot (OS) Level Hold (LH) Single-cycle level hold (S_LH) Complete-cycle level hold (C_LH) - Stop output signal setting - Serial, direct, or random trigger mode setting * Four frequency options (4/4.8/6/8 KHz) and LED On/Off control can be set independently in each GO instruction of speech equation * Independent control of LED 1 and LED 2 * Total of 256 voice group entries available for programming * Provides the following mask options: - LED flash type: synchronous/alternate - LED 1 section-controlled: Yes/No - LED 2 section-controlled/STPC-controlled - LED volume-controlled: No/Yes -2- W528XXX DESIGN GUIDE FUNCTIONAL DESCRIPTION 1. Instruction Sets The W528xxx family PowerSpeechTM program instruction sets include unconditional instructions and conditional instructions. Most of these instructions are programmed by writing "LD (Load)" and "JP (Jump)" commands and by modifying the content of the R0, EN, STOP, and MODE registers. Registers A. R0 Register R0 is an 8-bit register that stores the entry values of from 0 to 255 voice groups. The structure of this register is shown below: R0: Bit: B. EN Register EN is an 8-bit register that stores the rising/falling edge enable or disable status information for all trigger pins, which determines whether each trigger pin is retriggerable, non-retriggerable, overwrite, or non-overwrite. The 8-bit structure of this register and the rising or falling edge of the triggers corresponding to each bit are shown below: EN: Bit: Trigger: 7 4r 6 3r 5 2r 4 1r 3 4f 2 3f 1 2f 0 1f 7 6 5 4 3 2 1 0 The digits 1 to 4 represent triggers 1 to 4, respectively; "r" represents the rising edge; and "f" represents the falling edge. When any one of the eight bits is set to "1," the rising or falling edge of the corresponding trigger pin can be enabled, interrupting the current state. C. STOP Register The STOP register stores stop output status information to determine the voltage level of each stop output pin. The 8-bit structure of this register and the stop output pin corresponding to each bit are shown below: STOP: Bit: STOP: 7 X 6 X 5 X 4 X 3 X 2 STPC 1 STPB 0 STPA "X" indicates a "don't care" bit. D. MODE Register The MODE register is used to store operand information to select among various operating modes as shown below. 3- W528XXX DESIGN GUIDE MODE: Bit: MODE: 7 Flash/DC 6 LED2/STPC 5 TG4/LED2-STPC 4 Long / Short 3 X 2 X 1 X 0 X Bit 7 is used to determine the output status of LED1 and/or LED2: Flash alternate or synchronous output (by mask option), or DC (LED will be lit constantly without flash). Bit 6 and bit 5 together determine whether the I/O pin (i.e., pin 4) acts as a trigger input pin, LED output pin, or STOP output pin. Bit 4 is used to determine whether the debounce time for all trigger inputs is long ( around 45 mS ) or short ( around 350S). Commands A. Unconditional Instructions Load (LD) command: This command can load value or operand data into the R0, EN, STOP, or MODE register. LD R0, value: This instruction is used to load a voice group entry value into register R0, as shown in the following example. Example: LD R0, 167 (decimal) 0xA7 (hexadecimal) 1 0 1 0 0 1 1 1 B Value: 0 to 255 LD EN, operand: This instruction is used to define the trigger interrupt settings by loading the operand message into register EN. The following example illustrates how the settings are defined. Example: LD EN, 0x41 (hexadecimal) 0100 0001 (binary) 0 TG: Group: 4r 7 1 3r 6 0 2r 5 0 1r 4 0 4f 3 0 3f 2 0 2f 1 1 1f 0 a. When the rising edge of TG3 (3R) is activated, the EN register will cause TG3 to interrupt the current playing state and jump immediately to voice group 6, the voice group that corresponds to 3R. -4- W528XXX DESIGN GUIDE b. When the falling edge of TG1 goes active, the EN register will cause TG1 to interrupt the current playing state and jump immediately to voice group 0, the voice group that corresponds to 1F. c. No action will be taken when the other trigger pins are pressed, because the corresponding bits are set to "0." LD STOP, operand: This instruction loads the operand message into the STOP register to set the output levels of the stop signals. When a particular STOP bit is set to "1," the corresponding stop signal will be an active low output. Example: LD STOP, 0x43 0 STOP: X 1 X 0 X 0 X 0 X 0 STPC 1 STPB 1 STPA a. The STPA and STPB output signals will be high outputs. b. The STPC output signal will be a low output. c. The second bit "1" is a "don't care" bit and so has no effect on the stop signal output setting. LD MODE, operand: This instruction is used to select among various operating modes. It loads an operand message into the MODE register to select one mode from each of several pairs of modes. A "1" for one of these bits selects the first of the pair of modes indicated; a "0" selects the second of the pair. The following example describes the MODE setting of the W528xxx product. Example: LD MODE, 0xD0 1 1 0 1 0 0 0 0 MODE: Flash LED2 LED2-STPC Long don't care a. The LED is set as a flash type, with the flash frequency 3 Hz. b. Pin 4 (TG4/LED2-STPC) is configured as either the LED2 or STPC output (determined by bit 6, LED2/STPC). c. Pin 4 is configured as the LED2 output pin. d. The debounce time of the trigger inputs is set to long (around 45 mS). JUMP (JP) Command: JP value: 5- W528XXX DESIGN GUIDE Instructs device to jump directly to the voice group corresponding to the value indicated. The voice group value may range from 0 to 127. JP R0: Instructs device to jump to whatever voice group is indicated by the value currently stored in register R0. B. Conditional Instructions: Conditional instructions are executed only when the conditions specified in the instructions hold. The conditional instructions are listed below. An explanation of the notation used in the instructions follows. (Note: There are no conditional instructions for LD MODE.) Load (LD) command: LD R0, value @LAST: Load the voice group entry value into R0 when the last global repeat sound cycle is finished. LD R0, value @TGn_HIGH (or_LOW): If the n-th (n: 1 to 4) trigger pin status is kept at "High" (or "Low") voltage level, then load the value into R0 register. LD EN, operand @LAST: Load the operand message into EN register when the last global repeat sound cycle is finished. LD STOP, operand @LAST: Load the operand message into STOP register when the last global repeat sound cycle is finished. Jump (JP) command: JP value @LAST: When the last global repeat sound cycle is finished, jump to the group entry value indicated (range: 0 to 127) and begin execution. JP R0 @LAST: When the last global repeat sound cycle is finished, jump to the group entry value indicated by the R0 register and begin execution. -6- W528XXX DESIGN GUIDE JP value @TGn_ HIGH (or _LOW): _ If the n-th (n: 1 to 4) trigger pin is kept at "High" (or "Low") voltage level, then jump to the indicated value (range: 0 to 127) and begin execution. JP R0 @TGn_ HIGH (or _LOW): _ If the n-th (n: 1 to 4) trigger pin is kept at "High" (or "Low") voltage level, then jump to the group entry value indicated by the R0 register and begin execution. C. End Instruction: END: This command instructs the chip to cease all activity immediately. D. Instruction Set List: INSTRUCTION Unconditional LD R0, value LD EN, operand LD STOP, operand LD MODE, operand JP value JP R0 Conditional LD R0, value @LAST LD R0, value @TGn_HIGH LD R0, value @TGn_LOW LD EN, operand @LAST LD STOP, operand @LAST JP value @LAST RANGE 0-255 - - - 0-127 0-255 0-255 0-255 0-255 - - 0-127 DESCRIPTION R0 <-- value EN <-- operand STOP <-- operand MODE <-- operand Jump to the group entry value indicated Jump to the group entry indicated by R0 If last global repeat finished, R0 <-- value If TGn (n: 1-4) status is high level, R0 <-- value If TGn (n: 1-4) status is low level, R0 <-- value If last global repeat finished, EN <-- operand If last global repeat finished, STOP <-- operand If last global repeat finished, jump to the group entry value indicated If last global repeat finished, jump to the group entry value indicated in R0 If TGn (n: 1-4) status is high level, jump to the group entry value indicated If TGn (n: 1-4) status is low level, jump to the group entry value indicated DEFAULT VALUE 0000 0000 1111 1111 xxxx x111 1111 xxxx JP R0 @LAST 0-255 JP value @TGn_HIGH 0-127 JP value @TGn_LOW 0-127 7- W528XXX DESIGN GUIDE Instruction Set List, continued INSTRUCTION Conditional JP R0 @TGn_HIGH RANGE 0-255 DESCRIPTION If TGn (n: 1-4) status is high level, jump to the group entry value indicated in R0 If TGn (n: 1-4) status is low level, jump to the group entry value indicated in R0 Stop all activity and enter standby state DEFAULT VALUE JP R0 @TGn_LOW 0-255 END END - 2. Mask Option Description The mask options of the W528xxx PowerSpeechTM are used to select features that cannot be programmed through the chip's registers. The W528xxx provides four mask options, which are listed in the following table: MASK OPTION LED flash type (Asynchronous/Synchronous) LED volume controlled (No/Yes) LED1: section-controlled (Yes/No) LED2: section-controlled /STPC-controlled Notes: 1.The demo chip for the W528xxx series is the W5280. 2. The mask options can be configured automatically by the W5280. INSTRUCTION LED_ASYN; (default) LED_SYN LED_VOL_OFF; (default) LED_VOL_ON LED1_S_CTL; (default) LED1_S_OFF LED2_S_CTL; (default) LED2_STC_CTL DEMO CHIP OPTION - If LED_VOL_ON is set, the other mask options will be of no use - - 3. Speech Equation Description Speech equations are used to define the combination of playback sounds. The following is an example of the speech equation format: i: N H4+m1*Sound1_FL+m2*Sound2_FL+[1FFFF]+...T4 END -8- W528XXX DESIGN GUIDE where i defines the voice group number (from 0 to 255); N defines the number of global repeats (from 1 to 16); m1 and m2 define the number of local repeats (from 1 to 7); Sound1 and Sound2 are files containing ADPCM converted voice data; _FL is the section control setting, for which the parameters F and L are as follows: F Frequency L LED status 0 4 KHz 1 On 1 4.8 KHz 0 Off 2 6 KHz 3 8 KHz [1FFFF] is a period of silence of length 1FFFF. H4 and T4 are the Head file and Tail file with 4-bit ADPCM data format. These two files can be used to eliminate the popping sound when the sound starts and stops. The following is a sample waveform: V 1/2V H4 0.25Kbit T4 0.25Kbit 0 4. Programmable Power-on Initialization Whenever the W528xxx PowerSpeechTM is powered on, the programs contained in the 32nd voice group will be executed immediately. Thus the user can write programs into this group to set the initial power-on state. If the user does not wish to execute any programs at power-on, an "END" instruction should be entered in group 32. 5. PowerSpeechTM Program Format TM The W528xxx PowerSpeechTM enables users to define the functions of their products using the W528xxx PowerSpeechTM programming language. An example (for reference only) of the W528xxx PowerSpeechTM program format is shown below. (Explanatory notes follow the example.) 9- W528XXX DESIGN GUIDE (6) ; (default)/ [LED_SYN ] ; (default)/ [LED1_S_OFF ] ; (default)/ [LED2_STC_CTL ] ; (default)/ [LED_VOL_ON ] ; (default)/ [LED1 ] ; (default)/ [FREQ0, FREQ1, FREQ3 ] (1) W528S03 LED_ASYN LED1_S_CTL LED2_S_CTL LED_VOL_OFF LED0 FREQ2 (2) (3) (4) (5) 32: 5 (7) H4+SN_01+SN_20+SN_31+T4 (8) END 0: 3 H4+S11+S2+[1FFF]+T4 END 2: (9) LD R0, 64 ; disable all triggers LD EN, 0X00 LD MODE, 0X90 ; LED flash, Stop C, 45 mS LD STOP, 04 ; Stop C = 1, Stop A, Stop B = 0 END Notes: (1) Bodies: The user must first define the PowerSpeechTM body to be used, or else an error message will appear during compiling. The PowerSpeechTM bodies include the following: W528xxx: W528S03, W528S05, W528S08, W528S10, W528S12, W528S15, W528S20, W528S25, W528S30, W528S40, W528S50 and W528S60. (2) Mask Options: See page 8 above. (3) Declarations: State the output frequency and LED on/off state, as follows: LED on/off: LED0: LED off (default) LED1: LED on Output frequency: FREQ0: 4KHz FREQ1: 4.8 KHz FREQ2: 6 KHz (default) FREQ3: 8 KHz (4) Program body: Write application program and speech operations, including the following: Define entry point of speech group. Determine number of global repeats. Describe speech equations. Define the register values. (5) Group body: Define the voice group entry point. PRODUCT W528xxx GROUP ENTRY POINTS 0-255 TG H/W ENTRY POINTS 0-7 POWER-ON ENTRY POINT 32 (6) Note: A semicolon (";") is used to distinguish characters that are not part of the program. Characters written to the right of the semicolon are not considered part of the content of the program. - 10 - W528XXX DESIGN GUIDE (7) Global Repeat: The global repeat instruction is " n " where n is from 1 to 16. This instruction must be placed on the same line as the group entry point. The global repeat instruction can be represented in three ways, as shown below. 0: 3 H4+sound+T4 END 0: ; default = 1 H4+sound+T4 END (8) Speech equation: See page 8 and page 9 above. (9) Blank: A voice group entry point must be followed by one full blank line without any instructions or speech equations. The " n " instruction must follow the entry point, however. 6. Programming Examples (for reference only) This section presents several examples of how the functions of the W528xxx PowerSpeechTM may be programmed. Customer programs should be written in ASCII code using a text editor; after compiling, the sound effects resulting from the programs can be tested using a Winbond demo board. Example1: Four playing mode settings a. One-shot Trigger Mode 0: LD EN, 0X01 H4+sound+T4 END ; TG1 falling edge group entry point ; Enable TG1 falling edge input only The timing diagram for this example is shown below: CASE 1: TG1: AUD: Sound 1 CASE 2: TG1: AUD: Sound 1 11 - W528XXX DESIGN GUIDE b. Level Hold Trigger Mode 0: LD EN, 0X11 H4+sound1+T4 JP 0 4: END The timing diagram is shown below: ; TG1 rising edge group entry point ; TG1 falling edge group entry point ; Enable TG1 falling and rising edge input CASE 1: TG1: Stop immediately CASE 2: TG1: Stop immediately AUD: AUD: S1 S1 c. Completed Cycle Level Hold 0: LD EN, 0X01 H4+sound1+T4 JP 0 @TG1_LOW END The timing diagram is shown below: CASE 1: TG1: AUD: S1 ; TG1 falling edge group entry point ; Enable TG1 falling edge input only ; If TG1 state is low, jump to 0 entry point CASE 2: TG1: S1 S1 AUD: d. Single Cycle Level Hold 0: LD EN, 0X11 H4+sound1+T4 END 4: END The timing diagram is shown below: - 12 ; TG1 falling edge group entry point ; Enable TG1 falling and rising edge input W528XXX DESIGN GUIDE CASE 1: TG1: Stop immediately CASE 2: TG1: AUD: S1 AUD: Example 2: Retriggerable and Non-retriggerable setting a. Retriggerable: 0: LD EN, 0x01 . . . END . The timing diagram is shown below: TG1: AUD: Restart Restart Sound 1 Sound 1 b. Non-retriggerable: 0: LD EN, 0x00 . . . LD EN, 0x01 END The timing diagram is shown below: TG1: AUD: Sound 1 Sound 1 13 - W528XXX DESIGN GUIDE Example 3: Serial Playing Mode (5 segments) W528S03 32: (for reference only) LD R0, 8 LD EN, 0X01 END 0: JP R0 8: LD R0, 9 H4+S1+T4 END 9: LD R0, 10 H4+S2+T4 END 12: LD R0, 8 H4+S5+T4 END 11: LD R0, 12 H4+S4+T4 END 10: LD R0, 11 H4+S3+T4 END The timing diagram is shown below: TG1 1 2 3 5 1 AUD S1 S2 S3 S5 S1 Example 4: Random (1) W528S03 32: (for reference only) LD R0.8 LD EN,0X01 END 0: LD EN, 0X00 JP R0 8: JP 18 @TG1_HIGH 9: JP 19 @TG1_HIGH 20: H4+S3+T4 LD R0, 11 19: H4+S2+T4 LD R0, 8 JP 31 18: H4+S1+T4 LD R0, 9 JP 31 - 14 - W528XXX DESIGN GUIDE Example 4, continued 10: JP 20 @TG1_HIGH 11: JP 21 @TG1_HIGH JP 8 31: 21: JP 31 H4+S4+T4 LD R0, 10 LD EN, 0X01 END The timing diagram is shown below: TG1 1 2 3 5 1 ... ... AUD S3 S1 S4 S4 S2 Example 5: Random (2) W528S03 32: (for reference only) LD EN, 0X11 END 0: LD R0, 8 [100] LD R0, 9 [200] LD R0, 10 [300] LD R0, 11 [350] LD R0, 12 [300] JP 0 4: JP R0 12: H4+S2+T4 END 11: H4+S3+T4 END 10: H4+S5+T4 END 9: H4+S1+T4 END 8: H4+S4+T4 END 15 - W528XXX DESIGN GUIDE The timing diagram is shown below: TG1 1 2 3 5 1 ... ... AUD S5 S1 S3 S2 S4 7. Application Examples (for reference only) The following paragraph presents several special application examples. Example 1: Power-on Trigger: If one of the trigger pins is always grounded, then the sound corresponding to that trigger will be played out at power-on. Program: W528S03 32: (for reference only) LD EN, 0X00 JP 8 @TG1_LOW JP 9 @TG2_LOW JP 10 @TG3_LOW JP 11 @TG4_LOW LD EN, 0X0F 0: 8: H4+S1+T4 LD EN, 0X0F END 1: 3: 11: H4+S4+T4 LD EN, 0X0F END 2: 10: H4+S3+END LD EN, 0X0F END 9: H4+S2+T4 LD EN, 0X0F END - 16 - W528XXX DESIGN GUIDE Application Circuit: VDD TG1 TG2 TG3 TG4 AUD W528xxx LED1 STA STB Example 2: 8 TG Input Application: In this application, the 4 trigger inputs are expanded to 8 trigger inputs. Program: W528S03 32: (for reference only) LD MODE, 0XB0 LD STOP, 0X00 LD EN, 0X0F END 0: LD EN,0X00 LD STOP, 0X01 JP 8 @TG1_LOW LD STOP, 0X00 LD EN,0X0F H4+V2+T4 END 8: LD STOP, 0X00 LD EN,0X0F H4+V1+T4 END 1: LD EN,0X00 LD STOP, 0X01 JP 9 @TG2_LOW LD STOP, 0X00 ; STPA set to low level ; One Shot play mode ; disable trigger pin ; STPA set to high level ; check VSS ; STPA set to low level ; enable trigger pin ; play V2 ; pseudo trigger pin ; STPA set to low level ; enable trigger pin ; play V1 ; disable trigger pin ; STPA set to high level ; check VSS ; STPA set to low level 17 - W528XXX DESIGN GUIDE Example 2, Continued LD EN,0X0F H4+V4+T4 END 9: LD STOP, 0X00 LD EN,0X0F H4+V3+T4 END 2: LD EN,0X00 LD STOP, 0X01 JP 10 @TG3_LOW LD STOP, 0X00 LD EN,0X0F H4+V6+T4 END 10: LD STOP, 0X00 LD EN,0X0F H4+V5+T4 END 3: LD EN,0X00 LD STOP, 0X01 JP 10 @TG4_LOW LD STOP, 0X00 LD EN,0X0F H4+V8+T4 END 11: LD STOP, 0X00 LD EN,0X0F H4+V7+T4 END ; enable trigger pin ; play V4 ; pseudo trigger pin ; STPA set to low level ; enable trigger pin ; play V3 ; disable trigger pin ; STPA set to high level ; check VSS ; STPA set to low level ; enable trigger pin ; play V6 ; pseudo trigger pin ; STPA set to low level ; enable trigger pin ; play V5 ; disable trigger pin ; STPA set to high level ; check VSS ; STPA set to low level ; enable trigger pin ; play V8 ; pseudo trigger pin ; STPA set to low level ; enable trigger pin ; play V7 - 18 - W528XXX DESIGN GUIDE Application Circuit VDD V1 V2 V3 V4 V5 V6 V7 V8 TG4 LED1 STA STB TG3 AUD TG2 TG1 W528xxx Example 3: 12 TG Inputs Application Program: W528S03 32: (for reference only) LD MODE, 0XB0 LD STOP, 0X00 LD EN, 0X0F END LD EN, 0X00 LD STOP, 0X03 JP 10 @TG1_LOW LD STOP, 0X02 JP 11 @TG1_LOW LD STOP, 0X01 JP 12 @TG1_LOW LD STOP, 0X00 LD EN,0X0F END 1: LD EN, 0X00 LD STOP, 0X03 JP 20 @TG2_LOW LD STOP, 0X02 JP 21 @TG2_LOW ; disable all TGs ; STPA, STPB all set to 1 ; play V20 ; STPB, STPA = "10" ; play V21 ; pin4 set as TG4 pin ; set STPA and STPB = 0 0: ; disable all TGs ; STPA, STPB all set to 1 ; play V10 ; STPB, STPA = "10" ; play V11 ; STPB, STPA = "01" ; play V12 ; set STPA and STPB = 0 19 - W528XXX DESIGN GUIDE Example 3, Continued LD STOP, 0X01 JP 22 @TG2_LOW LD STOP, 0X00 LD EN,0X0F END 2: LD EN, 0X00 LD STOP, 0X03 JP 30 @TG3_LOW LD STOP, 0X02 JP 31 @TG3_LOW LD STOP, 0X01 JP 33 @TG3_LOW LD STOP, 0X00 LD EN,0X0F END 3: LD EN, 0X00 LD STOP, 0X03 JP 40 @TG4_LOW LD STOP, 0X02 JP 41 @TG4_LOW LD STOP, 0X01 JP 42 @TG4_LOW LD STOP, 0X00 LD EN,0X0F END 10: H4+V11+T4 LD STOP, 0X00 LD EN, 0X0F END 11: H4+V12+T4 LD STOP, 0X00 LD EN, 0X0F END ; STPB, STPA = "01" ; play V22 ; set STPA and STPB = 0 ; disable all TGs ; STPA, STPB all set to 1 ; play V30 ; STPB, STPA = "10" ; play V31 ; STPB, STPA = "01" ; play V33 ; set STPA and STPB = 0 ; disable all TGs ; STPA, STPB all set to 1 ; play V40 ; STPB, STPA = "10" ; play V41 ; STPB, STPA = "01" ; play V42 ; set STPA and STPB = 0 - 20 - W528XXX DESIGN GUIDE Example 3, Continued _ _ _ _ 41: H4+V41+T4 LD STOP, 0X00 LD EN, 0X0F END 42: H4+V42+T4 LD STOP, 0X00 LD EN, 0X0F END Application Circuit V10 V20 V30 V40 V11 V21 V31 V41 V12 V22 V33 V42 TG1 TG2 TG3 AUD W528xxx TG4 LED1 STA STB 21 - W528XXX DESIGN GUIDE Example 4: Power-on Reset Application If a product designer wants to use the POI (Power-On Initialize) function while adding a large capacitor between VDD and ground to eliminate voltage ripple or noise, then a discharge resistor must be added between VDD and ground. This discharge resistor prevents the system from hanging when the power is turned off and then on again. The application circuit is shown below: Application Circuit TG1 TG2 TG3 TG4 AUD W528xxx + VDD R Vss LED1 STA STB V R = 1 to 2 M if C is larger than 470 F. - 22 - |
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